1. Field of the Invention
The invention relates to a method of designing a layout of a semiconductor integrated circuit, a program for causing a computer to carry out the method, a method of fabricating a semiconductor integrated circuit, and an apparatus for designing a layout of a semiconductor integrated circuit.
2. Description of the Related Art
An internal circuit in a semiconductor integrated circuit such as LSI (Large Scale Integration) is accompanied with a problem that electrical noises generated when the internal circuit operates cause fluctuation in delay and malfunction.
For instance, such electrical noises are caused by fluctuation in a voltage of a power-source line, generated when a transistor is turned on or off.
Such electrical noises can be reduced by means of an on-chip capacitor arranged in LSI.
An on-chip capacitor is disposed usually in a vacant area formed between functional blocks disposed adjacent to each other. However, for instance, if such a vacant area is too small to place an on-chip capacitor therein, a fill-cell is placed in the vacant are in order merely to delete a space, namely, the vacant area.
For instance, Japanese Patent Application Publication No. 11-168177 (published June, 1999) has suggested a method of arranging a functional block and an on-chip capacitor in LSI.
FIG. 1 is a flow chart showing steps to be carried out in the method.
As illustrated in FIG. 1, first, functional blocks are placed so as to satisfy requirements such as connection indicated in a net list, a given delay, and a density of functional blocks, in step S201.
Then, there are fabricated on-chip capacitors each having a size equal to a size of each of spaces or vacant areas where functional blocks were not placed, and the thus fabricated on-chip capacitors are placed in the spaces, in step S202.
Then, fill-cells are placed in remaining spaces in which on-chip capacitors cannot be placed because the spaces are too small to place an on-chip capacitor therein, in step S203.
In the method shown in FIG. 1, a layout of the functional blocks is designed (step S201) before a layout of the on-chip capacitors is designed (step S202).
As described in the above-mentioned Publication, an on-chip capacitor is preferably disposed in the vicinity of a functional block in order to reduce electrical noises.
However, the method suggested in the above-mentioned Publication is accompanied with a problem that since an on-chip capacitor is disposed in a space where functional blocks have not been placed, it is not always for an on-chip capacitor to be disposed in the vicinity of a functional block, resulting in insufficient reduction in electrical noises.
In the method suggested in the above-mentioned Publication, as a density of functional blocks per a unit area becomes high, a lot of very small spaces or vacant area is formed between functional blocks. In order to place a functional block, a space has to have a certain width or area. However, since very small spaces exist a lot, it would not be possible to effectively arrange on-chip capacitors, resulting in insufficient reduction in electrical noises.
Japanese Patent Application Publication No. 7-106521 (published Apr. 21, 1995) has suggested a semiconductor integrated circuit device including a capacitor cell comprised of a N-channel MOS transistor having a gate terminal electrically connected to a power source, and a source terminal grounded, and a P-channel MOS transistor having a gate terminal grounded. The capacitor cell is mounted on a wiring area formed after automatic configuration and routing, ensuring that a bypass capacitor is accomplished in LSI.
Japanese Patent Application Publication No. 10-144797 (published May 29, 1998) has suggested a method of designing a semiconductor integrated circuit including a device formed on a semiconductor substrate, a plurality of electrically insulating layers and a plurality of wiring layers alternately formed above the semiconductor substrate, and via-contacts composed of electrically conductive material and filling therewith a plurality of via-holes formed throughout the electrically insulating layers, wherein wirings formed in different wiring layers from each other are electrically connected to each other through the via-contacts, and the device and a wiring formed in any one of the wiring layers are electrically connected to each other through the via-contacts, the method including the steps of selecting one of a current direction, a waveform of current, material of which a wiring is composed, material of which the via-contacts are composed, a wiring length, a wiring width, a wiring area, a wiring volume, a wiring thickness, and overlapping margin as a specific parameter affecting resistance to electromigration at an interface between the wirings and the via-contacts, dividing an allowable current in the via-holes into a plurality of zones in accordance with conditions relating to the specific parameter, selecting a typical current common to the zones, determining a typical current in a zone associated with the specific parameter, as an allowable current in each of the via-holes, and determining a total opening area of the via-holes and a shape of the wirings in accordance with the allowable current.
Japanese Patent Application Publication No. 2001-203272 (published Jul. 27, 2001) has suggested a method of designing a layout of a semiconductor integrated circuit, including the steps of designing a layout of functional blocks, a signal-line layout for electrically connecting the functional blocks to one another, and a wiring layout including a power-source wiring layout and a ground layout, filling a vacant area defined as an area except the functional block layout and the wiring layout with a dummy pattern for controlling an area rate, and fabricating a capacity layout including a plurality of capacity electrode layer layouts disposed in a dummy area filled with the dummy pattern, and electrically connected to one of the power-source wiring layout and the ground layout.